Here’s another installment of the great sci/tech stories from our guest writer, Ben Itzkowitz.
Samsung , a company producing some of the leading flash-memory chips in the world, has recently announced a new generation of chip that may be able to hold twice as much data as before without increasing circuit board size. Flash memory today uses a single layer of silicon that can store anywhere from a few megabits to a few gigabits of information. Researchers at Samsung have been able to prove that using multiple layers of silicon (instead of just one) is the key to creating more storage space on the memory. Today, we essentially use a 2-D structure in flash memory. By transferring over to 3-D architecture in the silicon layers, it is possible that one day in the near future a one-terabit flash chip composed of around 8 layers of silicon may begin use and production.
From mobile phones, to USB drives, to MP3 players and laptops, flash memory is found everywhere in our technological world today, greatly increasing the possible benefits of creating larger capacities in the same amount or less space. In recent years, it became popular for two different reasons. First off, it offered an alternative to spinning hard drives, which took up room and was generally very delicate. Since flash takes up much less room because it is solid-state memory, it also is much less prone to damage. The second reason is that it, unlike other types of solid-state memory such as random-access memory, is nonvolatile meaning it can retain data without power consumption. As already stated, silicon is what makes flash memory possible. Because silicon chip size has been consistently decreasing over recent years, so has flash drive memory. However, scientists predict that within the next few years, flash memory may begin to face fabrication hurdles because at a point, some things can only get so small before they are too small for practical use or too small to be manufactured correctly. Currently, flash memory chips contain features about 60 nanometers wide, and are fabricated with lithography machines that carve them out. Some engineers believe that the lithography systems needed to make the small etches in the silicon we use today will only be able to shrink until about 2009. Even then, if flash memory devices were to contain features on the silicon layers smaller than 30 nanometers in size, then the chips would face physical limitations such as leaking in the cell, also known as information loss.
Because of these future limitations, Samsung’s Soon-Moon Jung has begun to devise a way to use existing fabrication technology to increase flash capacity. He proposed that stacking the existing silicon layers on top of one another would do the trick. Two elements were required to do so according to Jung, which were minimizing the amount of extra area used for their stacking architecture, and keeping the number of fabrication steps down so as not to drive up costs. The technology would really work just like a parking lot where the lower level first fills up and it goes upwards from there. However, the only trouble found was that the structures to support the second layer of silicon (think in the parking garage the concrete columns) would take up valuable space otherwise used for storage. In order to decrease the space taken up by these supporting pieces, the “windows” that needed to be opened up to create them had to be strategically placed throughout the chip. Another trick that was used to create the second layer was to simultaneously fabricate the wire connections between the first and second layers. This ensured that costs would not rise because individually placing the connections would be more expensive to make. Although these technological obstacles were overcome, a different challenge in terms of performance came up that was much more difficult to maneuver around. Because of the second layer’s electrical nature (it isn’t grounded), only one cell of memory can be erased at once. On the other hand, larger chunks of memory cells can be erased at once on the first layer. By designing a specific electrical scheme that was able to ground the second layer as well, the data could then be erased in chunks there too. However, this extra component would also add to costs as well.
Although the prototype memory chip is only capable of a capacity of 32 bits so far, the results are very encouraging because they demonstrate the concept well and have successfully taken advantage of multiple layers of silicon in flash memory. The only hurdle that may need to be overcome in the future seems to be manufacturing costs. Obviously more silicon layers require more money, and since flash memory is driven by price, the larger quantities of storage might not be worth it if prices are too high. Possible solutions might be to mix different types of solid-state memory together or to engineer the layers of flash memory with even further minimized manufacturing steps. Over all, however, since Samsung can already utilize its existing 2-D flash memory manufacturing methods, much larger 3-D storage devices may be in store for the near future.